1. Technical Field
The present invention relates to methods and apparatuses for timing analysis of electronic circuits.
2. Background Information
Timing analysis in general is used in the context of analysis of electronic circuits, for example during the design of electronic circuits. In such electronic circuits, the timing of the circuit has to be checked such that signals generated by one circuit element reach another circuit element at an appropriate time. A simple example for this is some circuit element creating a signal which is to be sampled in a flip-flop controlled by a clock signal. The signal has to be present in a steady state at the flipflop a certain time before the sampling time defined by the clock signal (the so-called setup time) and a certain time after the sampling time defined by the clock signal (the so-called hold time) to ensure a correct sampling of the signal.
A more generalized version of this situation is shown in FIG. 1. FIG. 1 shows a so-called stage of an electronic circuit, for example a synchronous, digital circuit, wherein a signal is generated by a so-called driver cell 23 and passed to a receiver cell 25 via a network 24 which, as will be explained below, usually is a parasitic network. The driver cell 23 may, as indicated by a dashed arrow, also act as a receiver cell of a previous stage and generate the signal dependent on a further signal received. On the other hand, as also indicated by a dashed arrow, the receiver cell 25 may also act as a driver cell for a subsequent stage by sending a signal depending on the signal received from driver cell 23 via network 24.
It should be noted that the signal generated by driver cell 23 may be forwarded to a plurality of receiver cells like receiver 25 via network 24 or a plurality of networks. A single driver cell, the set of receiver cells receiving the signal from said driver cell and the network or networks coupling the driver to the set of receivers will, as already noted above, in the following be called a “stage”. An electronic circuit may be seen as a plurality of stages.
Network 24 is usually a network comprising capacitances, resistances, diodes and/or inductances, i.e. a passive network. The components of network 24 may in principle comprise components intentionally provided, like diodes for preventing excessive signal peaks, but in many cases is a parasitic network. Network 24, for example through RC elements, leads to distortions and/or delays of the signal from driver cell 23 to receiver cell 25. Driver cell 23 and receiver cell 25 have a structure depending on the electronic circuit to be examined and may for example comprise a plurality of transistors and other elements each.
It should be noted that very often in electronic circuits a driver cell like driver cell 23 or a receiver cell like receiver cell 25 has a plurality of inputs, also called input pins hereinafter. For example, receiver cell 25 may receive signals from a plurality of driver cells and would thus be part of a plurality of stages as explained above and may additionally receive external signal inputs which may also vary or be held constant.
As already explained, in electronic circuits it may be necessary that the signal from the driver cell reaches the receiver cell at a certain time, for example a certain time before and after a pulse of a clock signal fed to the receiver cell. Since modern integrated electronic circuits like microprocessors may comprise millions of transistors or, in terms of stages, thousands of stages or more, and these stages may be interrelated in a number of ways, tools are necessary to check and simulate the timing behavior of the electronic circuit before the actual implementation.
In principle, it is possible to employ so-called analog simulation to simulate the circuit. For analog simulations, usually each circuit element like transistors is represented by a set of differential equations, and these equations are solved for example using a time step method. Models for transistors which are employed in this respect often comprise over a hundred parameters. Therefore, with the computing power currently available, it is difficult to fully simulate whole circuits comprising millions of transistors for all possible combinations of inputs to the circuit, so-called input patterns, within a reasonable time frame. For example, conventional analog simulation has been able to simulate circuits comprising 50,000 transistors with a single input pattern.
Therefore, to perform a timing analysis the so-called static timing analysis (STA) is conventionally employed. In static timing analysis, the basic principle is to only consider “extremal” timing events and not to analyze all possible input patterns at the input terminals of a circuit design concurrently. In particular, no series of switchings at an input is analyzed, but only a single switching of one (or possibly more) input(s), while the remaining input(s) are held constant. Extremal timing events in this case are for example those input patterns which lead to the latest or earliest arrival of a signal at a given receiver cell. If these latest and earliest arrivals fulfill the timing requirements of the circuits, all other timing events are assumed to also fulfill the requirements. By using simplifications like the ones mentioned above, the computational effort of static timing analysis is linear with respect to the complexity of the design and not exponentially as it would be for a full analog simulation.
In conventional static timing analysis, a circuit design is broken down into the above-defined stages, and signal waveforms at the output terminals of a given stage are determined depending on signal waveforms at the input terminal of that stage. Accordingly, the circuit design is processed stage by stage according to a topological sorting of the stages starting at the input terminals of the design such that the required input signal for the next stage to be processed is available.
In conventional static timing analysis, to analyze the timing behavior of the signals, the receiver cells in a given stage are usually modeled as single capacitances which may be viewed as part of network 24 of FIG. 1.
Additionally, in conventional static timing analysis signal transitions from one state to another state (i.e. a transition between the two possible states of digital signals) are approximated as ramps, and a single voltage point is usually taken as a delay threshold for delay measurement of the transition. This situation is depicted in FIG. 2, where a signal 21 changes from logic 0 to a positive voltage VDD representing a logic 1. In the examplary diagram of FIG. 2, the ramp of signal 21 is chosen such that it crosses the actual signal which basically corresponds to curve 22 at voltages Vl, Vh. Vl may be set to 10% of VDD, and Vh may be set to 90% of VDD. The time between signal 21 reaching Vl and signal 21 reaching Vh is taken as a transition time, in the present case indicating the time necessary to change from a logic 0 to a logic 1. The delay threshold in the example shown is set to the point where signal 21 crosses VT=VDD/2, which time is designated t1 in FIG. 2. However, other values for VT may also be chosen. Through the approximations of signals as ramps, the signals may be characterized by a single parameter like the above-mentioned transition time or slew, or by a only few parameters.
However, true signal behavior may differ significantly from that. For example, a signal may have a shape as depicted by dashed line 22 in FIG. 2. As can be seen, the real signal waveform crosses the voltage VT at a different time t2, such that t1 is only an approximation missing the true value by Δt. When such deviations from the actual signal waveform become significant compared to the transition time, this leads to increasing inaccuracies of the timing analysis. For critical paths, i.e. paths were timing requirements are only barely fulfilled or barely not fulfilled, this may even lead to errors in the analysis.
Also, the representation of a receiver as a single capacitance as mentioned above is only an approximation, which also may lead to inaccuracies of the static timing analysis. In this respect, classic static timing analysis uses a library where the electrical characteristics of a plurality of possible driver cells, for example the behavior of the cells dependent on an input signal as characterized by the above-mentioned parameter(s) are stored. When evaluating a stage, the electrical characteristics of the driver cells are taken from that table, which also is an approximation.
Therefore, as circuits become more and more complex and timing in circuits often becomes more and more critical, there is a general need for methods and apparatuses for timing analysis of electronic circuits which improve the accuracy and which are still feasible in terms of computational effort.